1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a rewriting operation of a memory cell and a relieving operation of a defective memory cell in a semiconductor memory.
2. Description of Related Art
Many proposals have been made in a technology in which, when a defective memory cell is found out in a semiconductor memory, a suitable redundant memory cell is efficiently selected in place of the defective memory cell, and information to be stored in the defective memory cell is actually stored in the selected redundant memory cell, in order to avoid the above mentioned defect and to elevate the yield of production in the semiconductor memory.
For example, Japanese Patent Application Pre-examination Publication No. JP-A-03-104096 (an English abstract of JP-A-03-104096 is available from the Japanese Patent Office and the content of the English abstract of JP-A-03-104096 is incorporated by reference in its entirety into this application) proposes a semiconductor memory configured to prevent a plurality of output bits from failing simultaneously in order to elevate a bit relieving effect in a redundancy operation thereby to elevate reliability of the semiconductor memory. For this purpose, in a semiconductor memory of a m-bit input/output construction having a plurality of cell array columns, a plurality of sense amplifier columns, a row selection circuit provided for the plurality of sense amplifier columns, and a column selection circuit provided in common to the plurality of sense amplifier columns, the sense amplifier columns and cell array columns are divided into "m" groups in each of which a redundant sense amplifier and a redundant cell array are provided, and simultaneously, the column selection circuit is divided into "m" groups in each of which a redundant column selection circuit is provided.
Japanese Patent Application Pre-examination Publication No. JP-A-05-258591 (an English abstract of JP-A-05-258591 is available from the Japanese Patent Office and the content of the English abstract of JP-A-05-258591 is incorporated by reference in its entirety into this application) proposes a defective relieving method in which a redundant word line and an address comparing circuit/redundant decoder circuit are provided for each memory cell array block, and an address of a word line connected to a defective memory cell is programmed in an address comparing circuit provided in any memory cell block other than the memory cell array block including the defective memory cell, so that a defective word line is replaced by a redundant word line of the memory cell array block including the address comparing circuit thus programmed.
However, in technologies developed in this field of art including the above mentioned technologies, since it is a fundamental practice to select one word line, when an active operation such as a reading and a writing is executed, and when a rewriting operation called a refreshing is executed in a memory needing the refreshing, it is not possible to efficiently select a redundant circuit. With increase of memory cell arrays, since the number of word lines connected to the column selection line is increased, a load capacitance of the column selection line becomes large, resulting in an increased consumed current and in a lowered processing speed.
Here, a semiconductor memory capable of efficiently switch to a redundant circuit for a short time, is desired.
One example of the semiconductor memory is a synchronous DRAM having a construction as shown in FIGS. 4 and 5.
As shown in FIGS. 4 and 5, the semiconductor memory includes a plurality of memory cell arrays (for example, MAR0 to MAR3), each of which includes a main word line and two sub-word lines associated thereto, a plurality of memory cells connected to each of the sub-word lines being connected to the same bit line of the same sense amplifier in the same sub-word line set, and being alternately connected to the other bit line of the same sense amplifier in an adjacent other sub-word line set.
Now, a detailed construction of the above mentioned semiconductor memory will be described with reference to FIGS. 4 to 7. FIG. 4 is a block diagram illustrating one example of the above mentioned prior art synchronous DRAM, and FIG. 5 is a block diagram illustrating the construction of the memory cell arrays MAR0 to MAR 3 shown in FIG. 4.
In addition, FIG. 6 is a circuit diagram illustrating one example of the sub-word line driver circuit SWD shown in FIG. 5, and FIG. 7 is a circuit diagram illustrating one example of the replacement row address comparing circuit RED shown in FIG. 4. Incidentally, in the following description, for convenience of description it is assumed that the shown synchronous DRAM comprises four memory cell arrays, and the number of memory cells activated when a refresh command is inputted is four times the number of memory cells activated when an active command is inputted.
Furthermore, it is also assumed that when the refresh command is inputted, the main word lines M00 to M17 in all the memory cell arrays MAR0 to MAR3 are individually activated one by one. In FIG. 4, each of the memory cell arrays MAR0 to MAR3 includes a plurality of memory cells, and the memory cell arrays MAR0 to MAR3 operate independently of each other.
In the following, the construction of each memory cell array will be described. In FIG. 5, Reference Signs XD00 to XD17 designate main word line decoders, each of which is selected by a portion of an internal row address signal XI so as to drive a corresponding main word line M00 to M17.
Reference Signs RAD00 to RAD11 designate power supply line driving circuits, each of which is also selected by a portion of the internal row address signal XI so as to supply a power supply voltage to a power supply voltage supplying line RAI00 to RAI11.
On the other hand, Reference Sign SWD designates sub-word line driving circuits, each of which connected to a corresponding main word line M00 to M17 and a corresponding power supply voltage supplying line RAI00 to RAI11. When the corresponding main word line and the corresponding power supply voltage supplying line are selected, the sub-word line driving circuit SWD drives an associated sub-word line S0000 to S1007, and when at least one of the corresponding main word line and the corresponding power supply voltage supplying line is not selected, the sub-word line driving circuit SWD deactivates the associated sub-word line. Furthermore, Reference Sign RSWD designates redundant sub-word line driving circuits, each of which connected to a corresponding redundant main word line RXD0 to RXD7 and a corresponding power supply voltage supplying line RAI00 to RAI11. When the corresponding redundant main word line and the corresponding power supply voltage supplying line are selected, the redundant sub-word line driving circuit RSWD drives an associated redundant sub-word line RS00 to RS17, and when at least one of the corresponding redundant main word line and the corresponding power supply voltage supplying line is not selected, the redundant sub-word line driving circuit RSWD deactivates the associated redundant sub-word line.
Referring to FIG. 6 which is a circuit diagram illustrating one example of the sub-word line driver circuit SWD shown in FIG. 5, the main word line M00 is connected to a source of each of first and second transistors. The first transistor having the source connected to the main word line M00, has a gate connected to the power supply voltage supplying line RAI00, and a drain connected to a drain of a third transistor having a gate connected to another power supply voltage supplying line RAIB00 and a source connected to ground. The second transistor having the source connected to the main word line M00, has a gate to a high potential and a drain connected to a gate of a fourth transistor having a source connected to the power supply voltage supplying line RAI00 and a drain connected to the drain of the first transistor and the drain of the third transistor. The connection node between the third and fourth transistor is connected to a corresponding sub-word line S0000. The sub-word line driving circuits SWD are driven with the same power supply voltage supplying lines in common. Therefore, the main word line is connected to the sub-word line driving circuits SWD of the number corresponding to the column number of the sub-word line driving circuits SWD, and on the other hand, the power supply voltage supplying line RAI00 is connected to all the sub-word line driving circuits SWD included in each column of the sub-word line driving circuits SWD. Incidentally, "RAIB" indicates a signal complementary to the signal of the power supply voltage supplying line RAI, and is generated in the power supply voltage supplying line driving circuit RAD, but is omitted in FIG. 5 for simplification of the drawing.
The redundant sub-word line driving circuits SWD has the same construction as that of the sub-word line driving circuits SWD, excepting that the main word line M00 to M17 is replaced with the redundant main word line RXD0 to RXD7, and the sub-word line S0000 to S1007 is replaced with the redundant sub-word line RS00 to RS17. The power supply voltage supplying line RAI is used in common to the sub-word line driving circuits SWD.
The sub-word lines and the redundant sub-word lines are connected to corresponding memory cells, of memory cells which are denoted by small circles located in the form of a matrix in FIG. 5. When the sub-word line and the redundant sub-word line are activated, the memory cell is connected to a corresponding bit line, so that data is inputted or outputted through a sense amplifier.
In FIG. 4, a command decoder CDEC receives various command signals RAS, CAS, CS and WE supplied from an external, and generates, on the basis of the combination of the external command signals, internal command signals for determining an internal operation. Of the internal command signals, only an internal active command signal ACT and an internal refresh command signal RFSH, which relate to the present invention, are shown in FIG. 4.
The active command is a command for selecting and activating the sub-word line in order to input data into a memory cell from an external or in order to output data in the memory cell to the external. The refresh command is a command for rewriting the data of the memory cell.
In response to the internal active command signal ACT, an external address latch circuit ALAT fetches address signals A0 to An supplied from the external. A refresh address counter RCNT is a counter for holding a row address to be refreshed next, and updates the value of the counter in response to the internal refresh command signal RFSH.
An internal row address generating circuit XAD generates an internal row address signal XI which is based on an output of the external address latch circuit ALAT when the active command is inputted, and on the value of the refresh address counter RCNT when the refresh command is inputted. The internal row address signal XI is constituted of a plurality of binary bits, which can be divided into a plurality of groups each consisting of the same arbitrary number of digits. In FIG. 5, when the internal row address signal XI is divided into individual bits, the individual bits are designated with XI0, XI1, . . . , XIn, . . . .
In the case that the four memory cell arrays are provided as in the shown example, the ratio of the number of cells activated by the refresh command to the number of cells activated by the active command is four. In this case, the number of bits of the internal row address made effective when the refresh command is inputted is smaller than, by two bits, the bit number of the internal row address made effective when the active command is inputted. These two bits are used to distinguish or select one memory cell array, of the memory cell arrays MAR0 to MAR3, to be activated when the active command is inputted
Replacement row address comparing circuits RED0 to RE3 hold a row address of the sub-word line to be replaced with the redundant sub-word line, and compares the held row address with the internal row address signal.
FIG. 7 is a circuit diagram illustrating one example of the replacement row address comparing circuit RED. In FIG. 7, Reference Signs F0 to Fn designate two arrays of fuses, which can be cut off by a laser beam or other means.
In order to store the replacement row address, for example, either the fuse F0 or the fuse F1 is cut off. When the fuse F0 is cut the potential of a connection node NGDE does not change even if a bit XI0 of the internal row address signal is at a high level. However, when the internal address bit XI0 is at a low level, a transistor T1 is turned on in response to a complementary bit /XI0 of the bit XI0, so that the potential of the connection node NGDE is pulled down. This operation is executed for all the bits of the internal row address signal XI.
When the result of comparison made in this procedure does not indicate coincidence, a replacement discrimination signal REBL is inactivated, with the result that the main word line of the memory cell arrays MAR0 to MAR3 is activated on the basis of a portion of the internal row address signal XI. In addition, the power supply voltage supplying line RAI is selected on the basis of a portion of the internal row address signal XI.
On the other hand, when the result of comparison made in this procedure indicates coincidence, the replacement discrimination signal REBL is activated, with the result that the replacement is executed by activating the redundant main word line. The power supply voltage supplying line RAI is selected on the basis of the replacement discrimination signal REBL, and is not necessarily coincident with the selection on the basis of a portion of the internal row address signal XI when the replacement is not executed.
These operations are conducted in each of the memory cell arrays MAR0 to MAR3, independently of the other memory cell arrays. Accordingly, the memory cell arrays MAR0 to MAR3 can operate in parallel to each other.
Now, an operation will be described.
When the active command is inputted from the external, the internal active command signal ACT is generated, and the internal row address signal XI is generated on the basis of the address signals A0 to An supplied from the external.
Succeedingly, of the memory cell arrays MAR0 to MAR3, one memory cell array, for example, MAR0 is selected by the portion of the internal row address signal XI. The internal row address signal XI is also supplied to the replacement row address comparing circuits RED, and is compared with the replacement row address stored in the replacement row address comparing circuit RED.
If none of the replacement row address comparing circuits RED detects the coincidence, the main word line decoder designated by the portion of the internal row address signal, for example, XD00, is selected, so that the main word line M00 is driven.
Simultaneously, the power supply voltage supplying line driving circuits designated by the portion of the internal row address signal, for example, RAD00 and RAD01, are selected, so that the power supply voltage supplying lines RAI00 and RAI01 are driven.
As a result, the sub-word line driving circuits SWD000 and SWD010 are selected, so that the sub-word lines S000 and S010 are activated.
However, as mentioned above, since the power supply voltage supplying line driving circuits RAD00 and RAD01 generate signals complementary to each other, only one of the sub-word lines S000 and S010 is selected.
On the other hand, when any one of the replacement row address comparing circuits RED detects the coincidence, the redundant main word line decoder designated by the replacement row address comparing circuits RED having detected the coincidence, for example, RXD0, is selected, so that the redundant main word line RM0 is driven.
Simultaneously, the power supply voltage supplying line driving circuit designated by the replacement row address comparing circuits RED having detected the coincidence, for example, RAD10 or RAD11, is selected, so that the power supply voltage supplying line RAI10 or RAI11 is driven.
As a result, the redundant sub-word line driving circuits RSWD10 and RSWD11 are selected, so that the redundant sub-word line RS000 or RS0l0 are activated.
Furthermore, when the refresh command RFSH is inputted, all the memory cell arrays are selected, so that in each of the memory cell arrays, the sub-word lines or the redundant sub-word line are activated in substantially the same procedure as that executed when the active command is inputted.
Since each of the memory cell arrays MAR0 to MAR 3 include replacement row address comparing circuits RED operating independently of each other, the defective memory cell replacement is executed independently. Therefore, the same replacement efficiency as that obtained when the active command is inputted, can be obtained.
In the above mentioned operation, when the refresh command is inputted, since the memory cell arrays independently operate in parallel to each other, a total amount of the charging/discharging current of the sub-word lines, the charging/discharging current of the power supply voltage supplying lines and the charging/discharging current of the main word lines, becomes four times that when the active command is inputted.
Of these charging/discharging currents, the charging/discharging current of the sub-word lines are a current required in order to activate the sub-word lines of the number which is four times the number of the sub-word lines activated when the active command is inputted. However, comparing the main word lines with the power supply voltage supplying lines, the source electrode of the sub-word line driving circuits of the number larger that of the main word lines are connected to the power supply voltage supplying lines, and therefore, an interconnection capacitance and a parasite capacitance remarkably becomes large. This is a cause for remarkably increasing the current consumption when the refresh command is inputted.
In the above explanation, the case that only one main word line in each of the memory cell arrays MAR0 to MAR3 is activated, has been described. However, in order to elevate the replacement efficiency, it is possible to active a plurality of main word lines in each of the memory cell arrays MAR0 to MAR3.
In this case, the number of the activated power supply voltage supplying lines is not increased, increased of the charging/discharging current of the power supply voltage supplying lines is suppressed. In addition, if all the main word lines to be activated are included in the same memory cell array, the charging/discharging current of the power supply voltage supplying lines is not increased. Therefore, this modification may be preferable.
However, in this case, a plurality of sub-word lines of the sub-word lines connected to one power supply voltage supplying line are activated. Therefore, when a defective memory cell exists, it becomes impossible to replace only a portion of the plurality of sub-word lines to be activated, with the redundant sub-word line connected to another power supply voltage supplying line. Therefore, the replacement efficiency drops, with the result that the yield of production lowers.
In brief, in the above mentioned prior art example, if the case is considered in which the four memory cell arrays are provided and only one sub-word line is selected to be activated in one reading operation, when the one sub-word line has been discriminated to be defective, it is possible to arbitrarily select one of eight redundant sub-word lines of the redundant circuits. However, in an example in which two sub-word lines are simultaneously selected to be activated, if one of the two sub-word lines has been discriminated to be defective, it is possible to arbitrarily select one of only the three redundant circuits. Therefore, the number of the sub-word lines allocated for one power supply voltage supply line and activated when the active command is inputted, and the number of the sub-word lines allocated for one power supply voltage supply line activated when the refresh command is inputted, are in a tradeoff relation between the current consumption and the yield of production.
In the synchronous DRAM, generally, the number of sense amplifiers activated when the data is inputted or outputted in response to the active command, is different from the number of sense amplifiers activated when the memory is refreshed in response to the refresh command. For example, in a 256 M-bit synchronous DRAM having a 8K refresh cycle and four banks, 4K sense amplifiers are activated with the active command, and 16K sense amplifiers are activated with the refresh command.
Accordingly, the number of the sub-word lines (a gate electrode of memory cell transistors) activated when the active command ACT is inputted, is different from the number of the sub-word lines activated when the refresh command RFSH is inputted. In the above mentioned 256 M-bit synchronous DRAM, accordingly, when the refresh command RFSH is inputted, the sub-word lines of the number which is four times the number of the sub-word lines activated when the active command ACT is inputted, are activated.
On the other hand, since the power supply voltage is supplied to the sub-word lines S000 to S1007 by means of the power supply voltage supplying line driving circuits RAI, the number of the sub-word lines activated by one RAI line is the same, the charging/discharging current of the RAI line becomes large, so that the current consumption of the whole of a chip increases.
In particular, in the DRAM, since it is an ordinary practice to use an internal step-up system which elevates the activating voltage for the sub-word lines S000 to S1007, to a level higher than an external power supply voltage. In addition, since the internal step-up system is required to be designed to fulfill with a maximum consumption current, the chip area is inevitably increased.
Under this circumstance, it can be considered to change the number of the sub-word lines included in the sub-word lines connected to the same RAI line and activated when the active command is inputted, and the number of the sub-word lines included in the sub-word lines connected to the same RAI line and activated when the refresh command is inputted. This is possible by changing the number of activated main word lines orthogonal to the RAI lines. However, if this approach is adopted, the sub-word lines included in the same memory cell array and simultaneously activated when the refresh command is inputted, are required to be connected to the same RAI line. Therefore, if one defective line is included on these sub-word lines, when the defective line is replaced with a redundant sub-word line previously provided in the memory cell arrays, it is necessary to replace the defective line with the redundant sub-word line connected to the same RAI line. Therefore, the number of the defective sub-word lines to be replaced with the redundant sub-word lines is limited, so that the yield of production in the chip lowers.